1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, to a data input circuit of a semiconductor memory device.
2. Discussion of Related Art
In general, a data input circuit of a semiconductor memory device receives input data from an external device in synchronization with a data strobe signal. As described above, the data input circuit further receives the data strobe signal other than the externally input data from the external device.
FIG. 1 is a schematic block diagram of a data input circuit, a data output circuit, and an internal circuit of a semiconductor memory device in the related art.
Referring to FIG. 1, a data input circuit 10 and a data output circuit 30 are connected to an internal circuit 20 through a Global Input and Output (GIO) line 40. Though not shown in FIG. 1, the internal circuit 20 includes a core circuit having memory cells. FIG. 1 shows an example in which the data input circuit 10 receives 8-bit external input data DIN.
The data input circuit 10 includes a strobe buffer 11, a latch signal generator 12, a sensing controller 13, a data input buffer 14, a latch 15, a multiplexer 16, and an I/O Sense Amplifier (IOSA) 17.
As shown in FIGS. 1 and 2, the latch 15 latches bits of the input data DIN, which are serially inputted from the data input buffer 14, in response to latch control signals LCTL1 to LCTL8 received from the latch signal generator 12, and outputs latched data DLAT1 to DLAT8 in parallel. At this time, since the latch signal generator 12 generates the latch control signals LCTL1 to LCTL8 in synchronization with a strobe signal DQS, points of time at which the latch control signals LCTL1 to LCTL8 are toggled respectively may be varied when a point of time at which the strobe signal DQS is inputted to the data input circuit 10 is changed.
In more detail, skew may occur in the strobe signal DQS due to variation in parasitic capacitance existing between the semiconductor memory device including the data input circuit 10 and an external device (not shown) for transmitting the strobe signal DQS to the semiconductor memory device, or variation in PVT (i.e., process, voltage, and temperature) of the semiconductor memory device and the external device.
If skew is generated in the strobe signal DQS as described above, the point of time at which the strobe signal DQS is inputted to the data input circuit 10 may be varied. In other words, the strobe signal DQS may not be synchronized with a clock signal (i.e., a system clock signal CLK accurately and the phase of the strobe signal DQS may be faster or slower that the phase of the clock signal CLK.
For the purpose of the stabilized write operation of the semiconductor memory device, however, it is required that the strobe signal DQS be inputted to the strobe input buffer 11 within a predetermined time from a point of time at which a write instruction WRT is inputted to the semiconductor memory device. In other words, a point of time at which a first rising edge is generated after the strobe signal DQS is toggled must be included within the predetermined time.
To this end, in the specification of semiconductor memory devices, the range of a time (tDQSS); from a write command to a first rising edge of DQS) from a point of time at which the write instruction WRT is inputted to the semiconductor memory device to a point of time at which at which the first rising edge of the strobe signal DQS is generated is defied as a minimum time (tDQSSmin) and a maximum time (tDQSSmax).
When the time (tDQSS) of the strobe signal DQS is the minimum (i.e., tDQSSmin), the phase of the strobe signal DQS is t1 earlier than that of the clock signal CLK, as shown in FIG. 2. In contrast, when the time (tDQSS) of the strobe signal DQS is the maximum (i.e., tDQSSmax), the phase of the strobe signal DQS is t2 slower than that of the clock signal CLK. Consequently, a point of time at which the latch 15 outputs the latched data DLAT1 to DLAT8 when the time (tDQSS) is the minimum (i.e., tDQSSmin) is ΔT earlier than a point of time at which the latch 15 outputs the latched data DLAT1′ to DLAT8′ when the time (tDQSS) is the maximum (i.e., tDQSSmax).
As a result, a point of time at which the multiplexer 16 receives the latched data DLAT1 to DLAT8 and outputs data DMLX1 to DMLX8 to the IOSA 17 is earlier than a point of time at which the multiplexer 16 receives latched data DLAT1′ to DLAT8′ and outputs data DMLX1′ to DMLX8′ to the IOSA 17.
However, the IOSA 17 operates in synchronization with a sensing control signal DINST synchronized with the clock signal CLK regardless of the time (tDQSS). Accordingly, a point of time at which the IOSA 17 begins operating is fixed constantly. In this case, the clock signal CLK is generated by an internal clock generator (not shown) included in the semiconductor memory device having the data input circuit 10. Therefore, the clock signal CLK is stable and skew rarely occurs in the clock signal CLK.
As a result, although a point of time P1 or P2 at which the multiplexer 16 outputs the data DMLX1 to DMLX8 or DMLX1′ to DMLX8′ when the time (tDQSS) is the minimum (i.e., tDQSSmin) or the maximum (i.e., tDQSSmax) is changed, a point of time P5 at which the IOSA 17 begins performing the sensing and amplification operations (i.e., a point of time at which the sensing control signal DINST is enabled) is fixed to the clock signal CLK.
As a result, as shown in FIG. 2, a time t3 from the point of time P1 to the point of time P5 is longer than a time t4 from the point of time P2 to the point of time P5. Furthermore, times t5, t6 from a point of time P6 at which the sensing control signal DINST is disabled to points of time P3, P4 at which the data DMLX1 to DMLX8, DMLX1′ to DMLX8′ are respectively shifted are varied due to the difference between the times t3, t4. If the times t3 and t4 or t5 and t6 are varied as described above, data input margin cannot be secured.
As described above, the data input circuit 10 operates the IOSA 17 in synchronization with the clock signal CLK regardless of the time (tDQSS) of the data strobe signal DQS. Accordingly, a problem arises because data input margin cannot be secured stably.
The problem may become more profound in high-speed semiconductor memory devices operating at a relatively high frequency, such as Graphic Double Data Rate (GDDR) 4 Synchronous Dynamic Random Access Memory (SDRAM).
In other words, the high-speed semiconductor memory devices have data input margin lower than that semiconductor memory devices operating at a low frequency because the set-up and hold time margin of input data is reduced. The reduction in the data input margin may generate write operation fail of the semiconductor memory devices.